In recent years, with the increase of large display devices such as liquid crystal televisions, display devices have been actively developed. In specific, a technique of forming a driver circuit such as a gate driver over the same substrate as a pixel portion by using a transistor formed using a non-single-crystal semiconductor has been actively developed because the technique makes a great contribution for reduction in cost and improvement in reliability.
However, deterioration such as increase in threshold voltage or decrease in mobility is caused in the transistor formed using the non-single-crystal semiconductor. As the deterioration of the transistor advances, there is a problem in that the driver circuit becomes hard to operate and an image cannot be displayed. Accordingly, Patent Document 1 discloses a structure of a shift register which can suppress the deterioration of the transistor. In Patent Document 1, one electrode of a capacitor is connected to a wiring to which a clock signal is input and the other electrode of the capacitor is connected to gates of two transistors, so that the potential of the other electrode of the capacitor is increased or decreased by making the potential synchronize with the clock signal. In this manner, by utilizing capacitive coupling of the capacitor, signals that synchronize with the clock signal are generated in the gates of the two transistors. Then, by using the signals that synchronize with the clock signal, on and off of the transistors is controlled. Accordingly, since a period when the transistor is on and a period when the transistor is off are repeated, the deterioration of the transistors can be suppressed.
[Reference]
    [Patent Document 1] Japanese Published Patent Application No. 2006-24350
However, in Patent Document 1, since the other electrode of the capacitor is connected to the gates of the two transistors, there is a problem in that the parasitic capacitance of a node connected to the capacitor is high. Accordingly, there is a problem in that the potential in an H level of a signal that synchronizes with a clock signal becomes low. In that case, there is a problem in that a time during which a transistor can be turned is shortened if the threshold voltage of the transistor increases. That is, there is a problem in that the life of a shift register is shortened. Alternatively, since the parasitic capacitance of the node connected to the capacitor is high, there is a problem in that the capacitance value of the capacitor should be large. Accordingly, since an area where the one electrode of the capacitor and the other electrode of the capacitor overlap with each other needs to be large, there is a problem in that the layout area of the capacitor becomes large.
In Patent Document 1, since the area of the capacitor needs to be large, there is a problem in that short circuit between the one electrode and the other electrode tends to be caused due to dust or the like. As a result, there is a problem in that yield is decreased and cost is increased.
In Patent Document 1, since the capacitance value of the capacitor needs to be large, there is a problem in that delay or distortion of a signal (e.g., a clock signal or an inverted clock signal) supplied to the capacitor becomes obvious. Alternatively, there is a problem in that power consumption is increased.
Since a circuit having high current driving capability is used as a circuit for outputting a signal to be supplied to the capacitor, there is a problem in that an outside circuit (hereinafter also referred to as an external circuit) becomes large. Alternatively, there is a problem in that a display device becomes large.
In Patent Document 1, a period when a gate of a pull-up transistor Tu is in a floating state exists. Accordingly, noise or the like is caused because the potential of the gate of the pull-up transistor Tu is not stable. Therefore, there is a problem in that the shift register malfunctions.
In view of the foregoing problems, it is an object to decrease the number of transistors connected to a capacitor. Alternatively, it is an object to decrease the parasitic capacitance of a transistor connected to the capacitor. Alternatively, it is an object to increase the potential in an H level of a signal which synchronizes with a clock signal. Alternatively, it is an object to decrease a layout area. Alternatively, it is an object to extend life. Alternatively, it is an object to decrease delay or distortion of a signal. Alternatively, it is an object to reduce power consumption. Alternatively, it is an object to decrease the adverse effect of noise. Alternatively, it is an object to suppress or relieve deterioration of a transistor. Alternatively, it is an object to suppress malfunction. Alternatively, it is an object to prevent short circuit between one electrode of a capacitor and the other electrode of the capacitor. Alternatively, it is an object to decrease the current driving capability of an outside circuit. Alternatively, it is an object to reduce the size of an outside circuit. Alternatively, it is an object to reduce the size of a display device. Note that the descriptions of these problems do not disturb the existence of other problems.